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Mejora de la evaluación de expresiones regulares sobre hardware reconfigurable



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Muñoz Fernández, Claudio Alejandro (2011) Mejora de la evaluación de expresiones regulares sobre hardware reconfigurable. [Trabajo de curso] (No publicado)

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Since the Internet was born, the amount of data that systems process has increased in an exponential way and this is the reason because these systems need to be fast, flexible and powerful. Nowadays, communications keep increasing the speed requirements for data processing, and the FPGA‟s are ideal for this task.
In data processing, a huge amount of time is dedicated to pattern matching, frequently involving regular expressions matching. As the amount of patterns to be checked grow up, so does the hardware complexity dedicated to its recognition. Thus it needs to be flexible to be able to adapt to the necessary changes with ease.
In this project a VHDL code generator implemented in Java is presented. The code generated describes a regular expressions recognizer of various sets given by parameter, which will be synthetized by an FPGA. This module takes various sets of regular expressions and generates the VHDL code that describes the system which recognizes them.
The code generator is flexible, due to great modularity and upgradeability that software offers. Thus, the main advantage of this model consists on the possibility of combining the flexibility of software with the speed of hardware in order to create fast and low cost recognizers in a flexible and easy way.

Tipo de documento:Trabajo de curso
Información Adicional:

Proyecto de Sistemas Informáticos (Facultad de Informática, Curso 2010-2011)

Palabras clave:Regular expression matching, Pattern matching, Code generator, Regular expression optimization, Reconfigurable Hardware, Deep packet inspection, Networking, VHDL.
Materias:Ciencias > Informática > Hardware
Ciencias > Informática > Sistemas expertos
Código ID:13072
Depositado:23 Aug 2011 12:45
Última Modificación:06 Feb 2014 09:39

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