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Implementaciones hardware de circuitos aritméticos sobre cuerpos finitos (Hardwareimolementations of arithmetic circuits over finite field)

Sánchez Corrionero, Felipe (2011) Implementaciones hardware de circuitos aritméticos sobre cuerpos finitos (Hardwareimolementations of arithmetic circuits over finite field). Tesis Master's thesis.

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Abstract

La aritmética sobre cuerpos finitos ha recibido mucho interés debido a su importancia en criptografía, control de errores de codificación y procesado de señales digitales. Una gran parte del tiempo de las rutinas criptográficas se dedica al cálculo de operaciones aritméticas sobre cuerpos finitos. Los sistemas que usan esta aritmética deben ser
rápidos debido a los rendimientos requeridos en los sistemas de comunicación actuales. La suma en GF(2^m) es una operación XOR binaria independiente, puede ser realizada de forma rápida y sin retardo. Sin embargo otras operaciones son mucho más complejas y con mayor retardo. La eficiencia de las implementaciones hardware se mide en términos del número de puertas (XOR y AND) y del retardo total debido a esas puertas del circuito. El objetivo de este documento es hacer un estudio comparativo de diferentes circuitos aritméticos sobre GF(2^m), se utilizarán los cuerpos recomendados por el NIST y el SECG. Por su importancia, se han estudiado diferentes implementaciones para los algoritmos de multiplicación, tanto multiplicación serie como paralela junto con multiplicación dígito serie. Para el estudio de toras operaciones aritméticas, también se estudian algoritmos para obtener el cuadrado y el inverso de elementos pertencientes a GF(2^m). Para realizar este trabajo se implentarán los algoritmos mencionados en VHDL para FPGAs estudiando el consumo de área y tiempo de las operaciones comparando los resultados entre sí y con los obtenidos por otros autores. [ABSTRACT]Finite field arithmetic has received much attention due to its importance in cryptography, error control coding and digital signal processing. A large portion of time from
the routines of the cryptographies algorithms is used in the calculation of arithmetic operations on finite fields. Systems using this arithmetic must be faster because of
performance required in current communication systems. Addition in GF(2^m) is bit independent XOR operation, it can be implemented in fast and inexpensive ways. Nevertheless other operations are much more complex and expensive. The efficiency of the hardware implementations is measured in terms of the numbers of gates (XOR and AND) and of the total gate delay of the circuit. The aim of this document is to make a comparative study of different arithmetic circuits over GF(2^m), NIST and SECG recommended fields will be used. Due to multiplication is one of the most complex and important operation in finite field arithmetic, different implementations will be treated, parallel and serial along with digit-serial algorithms. To perform other operations, also inversion and square algorithms over GF(2^m)
have been discussed. VHDL implementations of these algorithms for FPGAs have been realized to study time and area consumption and to compare the result each other and with other authors'results.

Item Type:Thesis (Master's thesis)
Additional Information:Máster de Física Aplicada. Facultad de Ciencias Físicas. Curso 2010-2011
Directors:
DirectorsDirector email
Imaña Pascual, José Luis jluimana@dacya.ucm.es
Uncontrolled Keywords:Cuerpos Finitos, Cuerpos de Galois, Mastrovito, Dígito Serie, Aritmética, Fpga, Base Polinómica, Base Normal, Finite Fields, Galois Field, Mastrovito, Digit-serial, Arithmetic, Fpga-based, Polynomial Basis, Normal basis.
Subjects:Sciences > Physics > Mathematical physics
ID Code:13806
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Deposited On:15 Nov 2011 11:52
Last Modified:24 Nov 2011 09:46

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