Publication: Implementación hardware de un controlador de
memoria cache de reconfiguraciones en VHDL
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2014
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Abstract
Este proyecto presenta una implementación hardware de un controlador que gestiona de manera eficiente las reconfiguraciones que se realizan en tiempo de ejecución en un sistema que aplica cacheo de reconfiguraciones. Esta técnica consiste en utilizar una memoria on-chip que sirve de cache entre la memoria de configuración del dispositivo reconfigurable y la memoria principal, donde se guardarán todas y cada una de las reconfiguraciones que se quieran cargar en el dispositivo. La eficiencia de
la técnica se puede mejorar particionando las configuraciones en bloques, y mapeando las configuraciones en diferentes memorias cache, en vez de en una sola.
De este modo, dada una asignación de reconfiguraciones de tareas en diferentes memorias on-chip, el controlador hardware presentado gestiona la reconfiguración de las tareas de manera adecuada y eficiente. Los resultados experimentales que se presentan muestran que nuestro controlador realiza las operaciones necesarias en unos pocos cientos ciclos de reloj, mientras que su coste de implementación en términos de recursos hardware es muy asequible.
This project presents a hardware implementation of a controller that manages efficiently the run-time reconfigurations in a system that applies reconfiguration caching. This technique consists on using an on-chip memory that acts as a cache and that is placed between the reconfiguration memory of the device and the main memory where all the configurations are stored. The efficiency of this technique can be further improved by dividing the configurations into several blocks, each one of which can be mapped to a different on-chip memory. Thus, given a mapping of the configuration blocks on the different existing onchip memories, the hardware controller proposed manages the reconfiguration of these tasks in a proper and efficient way. The presented experimental results demonstrate that our module carries out the operations needed in just a few hundreds of clock cycles, while its implementation cost in terms of hardware resources is very affordable.
This project presents a hardware implementation of a controller that manages efficiently the run-time reconfigurations in a system that applies reconfiguration caching. This technique consists on using an on-chip memory that acts as a cache and that is placed between the reconfiguration memory of the device and the main memory where all the configurations are stored. The efficiency of this technique can be further improved by dividing the configurations into several blocks, each one of which can be mapped to a different on-chip memory. Thus, given a mapping of the configuration blocks on the different existing onchip memories, the hardware controller proposed manages the reconfiguration of these tasks in a proper and efficient way. The presented experimental results demonstrate that our module carries out the operations needed in just a few hundreds of clock cycles, while its implementation cost in terms of hardware resources is very affordable.
Description
Proyecto de Sistemas Informáticos (Facultad de Informática, Curso 2013-2014)