Universidad Complutense de Madrid
E-Prints Complutense

Customized Nios II multi-cycle instructions to accelerate block-matching techniques

Impacto

Downloads

Downloads per month over past year

González, Diego and Botella Juan, Guillermo and García Sánchez, Carlos and Meyer Bäse, Anke and Meyer Bäse, Uwe and Prieto Matías, Manuel (2015) Customized Nios II multi-cycle instructions to accelerate block-matching techniques. In SPIE 9400, Real-Time Image and Video Processing 2015, February 08, 2015, San Francisco, California, United States.

[img]
Preview
PDF
903kB

Official URL: http://dx.doi.org/10.1117/12.2077104



Abstract

This study focuses on accelerating the optimization of motion estimation algorithms, which are widely used in video coding standards, by using both the paradigm based on Altera Custom Instructions as well as the efficient combination of SDRAM and On-Chip memory of Nios II processor. Firstly, a complete code profiling is carried out before the optimization in order to detect time leaking affecting the motion compensation algorithms. Then, a multi-cycle Custom Instruction which will be added to the specific embedded design is implemented. The approach deployed is based on optimizing SOC performance by using an efficient combination of On-Chip memory and SDRAM with regards to the reset vector, exception vector, stack, heap, read/write data (.rwdata), read only data (.rodata), and program text (.text) in the design. Furthermore, this approach aims to enhance the said algorithms by incorporating Custom Instructions in the Nios II ISA. Finally, the efficient combination of both methods is then developed to build the final embedded system. The present contribution thus facilitates motion coding for low-cost Soft-Core microprocessors, particularly the RISC architecture of Nios II implemented in FPGA. It enables us to construct an SOC which processes 50×50 @ 180 fps.


Item Type:Conference or Workshop Item (Lecture)
Uncontrolled Keywords:Computer Vision, Optical Flow, MPEG Compression, Block Matching algorithm, NIOS II, FPGA, Custom Instructions, Embedded Systems
Subjects:Sciences > Computer science
Sciences > Computer science > Hardware
ID Code:31452
Deposited On:15 Jul 2015 12:31
Last Modified:16 Jul 2015 10:45

Origin of downloads

Repository Staff Only: item control page