Universidad Complutense de Madrid
E-Prints Complutense

Hardware Implementation of a Fault-Tolerant Hopfield Neural Network on FPGAs



Downloads per month over past year

Clemente Barreira, Juan Antonio and Mansour, Wassim and Ayoubi, Rafic and Serrano, Felipe and Mecha López, Hortensia and Ziade, Haissam and El Falou, Wassim and Velazco, Raoul (2016) Hardware Implementation of a Fault-Tolerant Hopfield Neural Network on FPGAs. Neurocomputing, 171 . pp. 1606-1609. ISSN 0925-2312


Official URL: http://0-www.sciencedirect.com.cisne.sim.ucm.es/science/article/pii/S0925231215008760


This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non fault- tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.

Item Type:Article
Uncontrolled Keywords:Artificial Neural Network (ANN), Hopfield Neural Network (HNN), Single Event Upset (SEU), Single Event Transient (SET), FPGA, Fault tolerance
Subjects:Sciences > Computer science > Hardware
ID Code:39057
Deposited On:08 Sep 2016 11:27
Last Modified:19 Sep 2016 10:09

Origin of downloads

Repository Staff Only: item control page