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A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems

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Clemente Barreira, Juan Antonio and Resano, Javier and González Calvo, Carlos and Mozos Muñoz, Daniel (2011) A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19 (7). pp. 1263-1276. ISSN 1063-8210

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Official URL: http://dx.doi.org/10.1109/TVLSI.2010.2050158



Abstract

New generation embedded systems demand high performance, efficiency and flexibility. Reconfigurable hardware can provide all these features. However the costly reconfiguration process and the lack of management support have prevented a broader use of these resources. To solve these issues we have developed a scheduler that deals with task-graphs at run-time, steering its execution in the reconfigurable resources while carrying out both prefetch and replacement techniques that cooperate to hide most of the reconfiguration delays. In our scheduling environment task-graphs are analyzed at design-time to extract useful information. This information is used at run-time to obtain near-optimal schedules, escaping from local-optimum decisions, while only carrying out simple computations.
Moreover, we have developed a hardware implementation of the scheduler that applies all the optimization techniques while introducing a delay of only a few clock cycles. In the experiments our scheduler clearly outperforms conventional run-time schedulers based on As-Soon-As-Possible techniques. In addition, our replacement policy, specially designed for reconfigurable systems, achieves almost optimal results both regarding reuse and performance.


Item Type:Article
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© © 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Uncontrolled Keywords:Field Programmable Gate Arrays, Reconfigurable Architectures, Task scheduling
Subjects:Sciences > Computer science > Hardware
ID Code:39459
Deposited On:13 Oct 2016 12:23
Last Modified:14 Oct 2016 08:08

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