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A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems

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Clemente Barreira, Juan Antonio and González, Carlos and Resano, Javier and Mozos Muñoz, Daniel (2008) A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems. In Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on, 3-5 Dec. 2008.

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Official URL: http://dx.doi.org/10.1109/ReConFig.2008.31



Abstract

Reconfigurable hardware can be used to build a multitasking system where tasks are assigned to HW resources at run-time according to the requirements of the running applications. These tasks are frequently represented as direct acyclic graphs and their execution is typically controlled by an embedded processor that schedules the graph execution. In order to improve the efficiency of the system, the scheduler can apply prefetch and reuse techniques that can greatly reduce the reconfiguration latencies. For an embedded processor all these computations represent a heavy computational load that can significantly reduce the system performance. To overcome this problem we have implemented a HW scheduler using reconfigurable resources. In addition we have implemented both prefetch and replacement techniques that obtain as good results as previous complex SW approaches, while demanding just a few clock cycles to carry out the computations. We consider that the HW cost of the system (in our experiments 3% of a Virtex-II PRO xc2vp30 FPGA) is affordable taking into account the great efficiency of the techniques applied to hide the reconfiguration latency and the negligible run-time penalty introduced by the scheduler computations.


Item Type:Conference or Workshop Item (Lecture)
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© © 2008 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Uncontrolled Keywords:FPGAs, Reconfigurable architectures, Task scheduling, Hardware multitasking
Subjects:Sciences > Computer science > Hardware
ID Code:39551
Deposited On:21 Oct 2016 10:12
Last Modified:21 Oct 2016 10:12

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