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Reliability Improvement of Hardware Task Graphs via Configuration Early-fetch

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Ramezani, Reza and Sedaghat, Yasser and Clemente, Juan Antonio (2017) Reliability Improvement of Hardware Task Graphs via Configuration Early-fetch. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25 (4). pp. 1408-1420. ISSN 1063-8210

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Official URL: http://ieeexplore.ieee.org/document/7779146/



Abstract

This study presents a technique to improve the reliability and the Mean Time to Failure (MTTF) of hardware task graphs running on reconfigurable computers. This tech- nique, which has been named Task Early-fetch, can be applied to a sequence of one or several applications, represented as task graphs. It consists in carrying out the reconfiguration of some tasks within the execution of the previous task graph, plus increasing the redundancy level of the early-fetched tasks. Experimental results on actual task graphs show the positive impacts of the proposed technique. Thus, without deteriorating the execution time (makespan), on average, a 114% MTTF improvement is achieved for no-fault-tolerant task graphs, and the improvement is more significant when applying to fault- tolerant task graphs. Finally, this paper presents a hardware implementation of a manager that applies these techniques at run-time and steers the execution of the running task graphs. It demonstrates that, with 0.03% consumption of FFs and LUTs and also 1.22% occupancy of BRAMs available on a Xilinx Virtex UltraScale XCVU095-2FFVA2104E FPGA, the required run-time computations can be carried out in negligible delays.


Item Type:Article
Uncontrolled Keywords:FPGAs, Reliability, Task Graph, Scheduling, Early-fetch, Fault Tolerance
Subjects:Sciences > Physics > Nuclear physics
Sciences > Computer science > Integrated circuits
Sciences > Computer science > Hardware
Sciences > Computer science > Electronics
ID Code:44680
Deposited On:19 Sep 2017 15:57
Last Modified:20 Sep 2017 08:08

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