Universidad Complutense de Madrid
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Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA

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Olivito, Javier y Serrano, Felipe y Clemente, Juan Antonio y Mecha, Hortensia y Resano, Javier (2018) Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA. IET Computers & Digital Techniques . pp. 1-33. ISSN 1751-8601 (En prensa)

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URL Oficial: http://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2016.0095



Resumen

In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. We have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead.


Tipo de documento:Artículo
Materias:Ciencias > Informática > Circuitos integrados
Ciencias > Informática > Hardware
Ciencias > Informática > Electrónica
Código ID:46629
Depositado:02 Mar 2018 09:43
Última Modificación:05 Mar 2018 09:33

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