Publication: Emulación basada en FPGA de los efectos de los single event upsets ocasionados por la radiación en circuitos digitales tolerantes a fallos
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2018-10-29
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Universidad Complutense de Madrid
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Abstract
Esta investigación explora los efectos de la radiación cósmica en circuitos digitales. El trabajo está dividido en dos partes. La primera parte de este trabajo se centra en poder emular uno de los efectos más comunes causados por dicha radiación: los Single Event Upsets (SEUs). La emulación de SEUs se realiza en dispositivos reconfigurables como son las FPGAs, ya que han ganado especial relevancia en sectores donde la radiación está presente, como son el sector aeroespacial y el de defensa. Esto es debido a las características tan beneficiosas que ofrecen en cuanto a consumo, flexibilidad, coste y prestaciones. Por ello, el principal objetivo ha sido aportar una herramienta de emulación de SEUs que no tenga las limitaciones del resto de herramientas existentes en el estado del arte. Esto significa que la herramienta debe ser no intrusiva, determinista y eficiente. La segunda parte de esta tesis doctoral, se ha centrado en explorar nuevas técnicas y metodologías en el ámbito del diseño digital tolerante a fallos para poder enfrentarse a la problemática que supone trabajar en entornos radiactivos. El resultado de este trabajo es una herramienta llamada NESSY, que permite inyectar errores en los distintos elementos de memoria de diseños digitales, emulando de esta manera a los SEUs. Debido a la heterogeneidad de las FPGAs, la manera de realizar dichas inyecciones difiere en función del tipo de elemento de memoria que pueda ser afectado por la radiación. Por lo tanto, se distinguen dos casos dependiendo de si el elemento de memoria pertenece a la memoria de configuración del dispositivo, o de si este elemento es un flipflop del propio circuito (común a cualquier diseño digital). Por este motivo, NESSY implementa dos metodologías para inyectar un error. La primera, realiza la inyección del error en bits de la memoria de configuración de las FPGAs, siendo una inyección eficiente, no intrusiva y determinista. Dicha metodología tiene cabida cuando se trabaja con circuitos implementados en FPGAs puesto que la memoria de configuración es propia de estos dispositivos. Para complementar a la primera, existe la segunda metodología que permite inyectar errores en flipflops. La inyección en flipflops también se realiza de manera eficiente y determinista pero se ha tenido que sacrificar la característica de no intrusividad, con el fin de poder mantener la eficiencia. Dicha metodología es aplicable a cualquier circuito digital y no se limita a los implementados en FPGAs. Esto supone el que sea posible evaluar la vulnerabilidad frente a SEUs de un diseño antes de su fabricación, traduciéndose en un beneficio tanto económico como de calendario. Gracias al desarrollo de esta herramienta, ha sido posible avanzar en la otra línea principal de esta investigación: el estudio de nuevas técnicas de protección de circuitos. Primero, se han decidido probar diferentes variantes de un método de protección de circuitos bien conocido y validado: la triple redundancia modular (TMR), con el fin de validar la herramienta. Para ello, se han realizado distintas campañas de inyección de errores a un conjunto de circuitos cuando éstos no tenían protección alguna (diseño original), y con distintos niveles de protección basados en la técnica TMR para poder comprobar así, que efectivamente los resultados obtenidos son consistentes a la protección esperada por dicha técnica. A continuación, se han desarrollado técnicas de protección novedosas para familias de circuitos específicas. La primera de ellas se centra en circuitos basados en redes neuronales de tipo Hopfield (HNN) y se basa en aplicar una redundancia parcial inteligente para obtener mejores resultados que los ofrecidos por el TMR. La segunda técnica de protección investigada se centra en circuitos que utilizan módulos hardware de propósito específico conocidos como procesadores digitales de señal (DSPs). Existen multitud de circuitos que hacen gran uso de operaciones aritméticas que puede beneficiarse de dicha técnica.
This research explores the effects of cosmic radiation on digital circuits. The work is divided in two differentiated parts. The fist one focuses on the emulation of one of the most typical effects caused by radiation: the Single Event Upsets (SEUs). The emulation of the SEUs is carried out on reconfigurable devices such as FPGAs. Said devices have obtained special relevance in sectors where radiation is an issue, such as aerospace and defense. This relevance is due to their useful features involving power consumption, flexibility, cost and performance. The objetive has been to presesnt a fault injection tool that circumvents the limitations of other similar tools in the state of the art, especially in terms of nonintrusiveness and performance. In other words, it has to be non-intrusive, deterministic and efficient. The second part of the doctoral thesis explores new techniques and methodologies in the field of fault tolerant digital circuits in order to palliate the problems related to working in radioactive environments. The result of this work is a tool called NESSY, which allows to emulate SEUS by means of injecting errors in the memory cells of digital designs. The FPGAs are heterogeneous, so the method to carry out the fault injections is different depending of the type of memory cell that can be affected by radiation. Thus, two possible cases exist: 1) the memory cell belongs to the configuration memory of the device and 2) the memory cell is actually a flipflop in the circuit (present in every digital design). Because of that, NESSY implements two methodologies to inject an error. The first one makes the injection in the bits of the configuration memory of the FPGA in a non-intrusive, efficient and deterministic way. This methodology can be used only when the target circuit is implemented using a FPGA because this kind of memory is present only in such devices. The second methodology makes NESSY able to inject faults in flipflops. This method is also efficient and deterministic; however, the non-instrusiveness feature had to be eliminated in order to be able to keep it efficient. This second methodology is applicable to every digital design and thus, it is not limited to implementations in FPGAs. These two methodologies altogether allow evaluating the vulnerability of any circuit against SEUs, prior to manufacturing it, thereby saving money and time. Thanks to the developed tool NESSY, it has been possible to move towards the other main line of the research of this doctoral thesis: the study of new circuit protection techniques. First of all, a well-known protection technique has been tested: the Triple Modular Redundancy (TMR), in order to validate NESSY. For that purpose, several injection campaigns has been carried out on a set of circuits. These circuits have been used with different levels of protection, ranging from the original ones (unprotected, and thus vulnerable to SEUs) to several levels of protection based in TMR. Then, two novel new protection techniques for specific families of circuits have been presented and validated. The first one is used with Hopfield Neural Networks (HNN) and it consists in applying intelligent and partial redundancy to obtain an implementation nearly as robust as a triplicated design, but that considerably reduces its resources consumption. The second technique can be applied to circuits that use specific purpose hardware modules known as Digital Signal Processors (DSPs). There exist a lot of circuits that perform intensive arithmetic operations that can benefit from this technique.
This research explores the effects of cosmic radiation on digital circuits. The work is divided in two differentiated parts. The fist one focuses on the emulation of one of the most typical effects caused by radiation: the Single Event Upsets (SEUs). The emulation of the SEUs is carried out on reconfigurable devices such as FPGAs. Said devices have obtained special relevance in sectors where radiation is an issue, such as aerospace and defense. This relevance is due to their useful features involving power consumption, flexibility, cost and performance. The objetive has been to presesnt a fault injection tool that circumvents the limitations of other similar tools in the state of the art, especially in terms of nonintrusiveness and performance. In other words, it has to be non-intrusive, deterministic and efficient. The second part of the doctoral thesis explores new techniques and methodologies in the field of fault tolerant digital circuits in order to palliate the problems related to working in radioactive environments. The result of this work is a tool called NESSY, which allows to emulate SEUS by means of injecting errors in the memory cells of digital designs. The FPGAs are heterogeneous, so the method to carry out the fault injections is different depending of the type of memory cell that can be affected by radiation. Thus, two possible cases exist: 1) the memory cell belongs to the configuration memory of the device and 2) the memory cell is actually a flipflop in the circuit (present in every digital design). Because of that, NESSY implements two methodologies to inject an error. The first one makes the injection in the bits of the configuration memory of the FPGA in a non-intrusive, efficient and deterministic way. This methodology can be used only when the target circuit is implemented using a FPGA because this kind of memory is present only in such devices. The second methodology makes NESSY able to inject faults in flipflops. This method is also efficient and deterministic; however, the non-instrusiveness feature had to be eliminated in order to be able to keep it efficient. This second methodology is applicable to every digital design and thus, it is not limited to implementations in FPGAs. These two methodologies altogether allow evaluating the vulnerability of any circuit against SEUs, prior to manufacturing it, thereby saving money and time. Thanks to the developed tool NESSY, it has been possible to move towards the other main line of the research of this doctoral thesis: the study of new circuit protection techniques. First of all, a well-known protection technique has been tested: the Triple Modular Redundancy (TMR), in order to validate NESSY. For that purpose, several injection campaigns has been carried out on a set of circuits. These circuits have been used with different levels of protection, ranging from the original ones (unprotected, and thus vulnerable to SEUs) to several levels of protection based in TMR. Then, two novel new protection techniques for specific families of circuits have been presented and validated. The first one is used with Hopfield Neural Networks (HNN) and it consists in applying intelligent and partial redundancy to obtain an implementation nearly as robust as a triplicated design, but that considerably reduces its resources consumption. The second technique can be applied to circuits that use specific purpose hardware modules known as Digital Signal Processors (DSPs). There exist a lot of circuits that perform intensive arithmetic operations that can benefit from this technique.
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Tesis inédita de la Universidad Complutense de Madrid, Facultad de Informática, Departamento de Arquitectura de Computadores y Automática, leída el 22/06/2017.