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A machine learning-based framework for throughput estimation of time-varying applications in multi-core servers

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Iranfar, Arman and Souza, Wellington Silva de and Zapater, Marina and Olcoz Herrero, Katzalin and Souza, Samuel Xavier de and Atienza, David (2019) A machine learning-based framework for throughput estimation of time-varying applications in multi-core servers. In 2019 IFIP/IEEE 27th International conference on very large scale integration (VLSI-SOC). IEEE-IFIP International Conference on VLSI and System-on-Chip . IEEE, Nueva York, pp. 211-216. ISBN 978-1-7281-3915-9

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Official URL: http://dx.doi.org/10.1109/VLSI-SoC.2019.8920309


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Abstract

Accurate workload prediction and throughput estimation are keys in efficient proactive power and performance management of multi-core platforms. Although hardware performance counters available on modern platforms contain important information about the application behavior, employing them efficiently is not straightforward when dealing with time-varying applications even if they have iterative structures. In this work, we propose a machine learning-based framework for workload prediction and throughput estimation using hardware events. Our framework enables throughput estimation over various available system configurations, namely, number of parallel threads and operating frequency. In particular, we first employ workload clustering and classification techniques along with Markov chains to predict the next workload for each available system configuration. Then, the predicted workload is used to estimate the next expected throughput through a machine learning-based regression model. The comparison with state of the art demonstrates that our framework is able to improve Quality of Service (QoS) by 3.4x, while consuming 15% less power thanks to the more accurate throughput estimation.


Item Type:Book Section
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©2019 IEEE
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)(27. 2019. Cuzco, Perú)
ISSN 2324-8432
This work has been supported by Spanish MINECO (GA. No. TIN2015-65277-R), the Spanish MINECO (GA. No. S2018/TCS-4423), the SERI Seed Money project (GA No. SMG1702), the EC H2020 RECIPE project (GA No. 801137), and the ERC Consolidator Grant COMPUSAPIEN (GA No. 725657).

Uncontrolled Keywords:Ingeniería; Eléctrica; Electrónica
Subjects:Sciences > Computer science > Artificial intelligence
ID Code:60291
Deposited On:01 May 2020 20:43
Last Modified:08 May 2020 18:07

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