Publication: Generación de cores basados en RISC-V y exploración arquitectónica de las memorias caché usando Rocket Chip Generator
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2020
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Abstract
En este trabajo se explora la arquitectura RISC-V, el core Rocket que la implementa y la herramienta Rocket-chip que nos permite diseñar microarquitecturas y generar un emulador de estas. Estos emuladores simulan la ejecución ciclo a ciclo de un programa en dichas microarquitecturas.
Posteriormente, se crean programas para explorar las propiedades de las cachés de datos de los diseños generados y se ejecutan dichos programas sobre los emuladores para realizar mediciones de rendimiento y sacar los resultados consecuentes.
This work explores the RISC-V architecture, the Rocket core that implements it and the Rocket-chip tool that allows us to design microarchitectures and generate an emulator of these. These emulators simulate the cycle-by-cycle execution of a program in said microarchitectures. Subsequently, programs are created to explore the properties of the data caches of the generated designs and these programs are run on the emulators to perform performance measurements and obtain the consequent results.
This work explores the RISC-V architecture, the Rocket core that implements it and the Rocket-chip tool that allows us to design microarchitectures and generate an emulator of these. These emulators simulate the cycle-by-cycle execution of a program in said microarchitectures. Subsequently, programs are created to explore the properties of the data caches of the generated designs and these programs are run on the emulators to perform performance measurements and obtain the consequent results.
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Trabajo de Fin de Grado en Ingeniería Informática, Facultad de Informática UCM, Departamento de Arquitectura de Computadores y Automática, Curso 2019/2020.