Publication: Evaluación de nodos basados en RISC-V para su uso en aplicaciones IoT
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2021-09-21
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Abstract
A cada día que pasa el mercado IoT (y AIoT) crece más, y con este crecimiento crece también la repercusión de la tecnología en nuestra vida. Desde el teléfono en el bolsillo hasta neveras inteligentes, la vida humana está cada día más conectada a internet, con los beneficios y riesgos que conlleva. Estos dispositivos pueden contar con la suerte de tener software de código abierto que permita ver que es lo que el aparato realmente hace a nivel de software. Pero respecto al hardware no se puede realmente saber que está pasando a no ser que el fabricante decida liberar su diseño. Ahí entra RISC-V, una arquitectura libre.
RISC-V es una arquitectura libre. A diferencia de sus competidores, el desarrollo del chip no empieza pagando (millonarias) licencias, permiten mayor innovación al ser más accesible, tanto económicamente como tecnológicamente y permiten que los ojos de toda la comunidad realicen una auditoría de seguridad extra como ya sucede en el mundo del software de codigo abierto.
En este trabajo se evalúan dos nodos basados en RISC-V. Cada nodo tiene el chip Kendryte K210, que es el componente basado en dicha arquitectura. En este trabajo se describen las características del hardware, herramientas a utilizar, puesta a punto del entorno y desarrollo sobre estos dispositivos para terminar con una reflexión sobre sus capacidades y facilidad de uso.
Every day the IoT (and AIoT) market grows, and with this growing the impact of the technology in our lives gets bigger. From the phones in the pocket to the smart fridges, the connection of human daily life to internet is constantly expanding, with the benefits and risk that it takes within. These devices may work with open source software, so the user is totally aware of what is going on at a software level. However, the same cannot be said about the hardware unless the manufacturer decides to release the design. That’s where RISC-V comes in, an open ISA (Instruction Set Architecture). RISC-V is an open ISA. Unlike its competitors, the development of the chip does not start by paying (million dollar) licenses, it allows more innovation by being more accessible, both economically and technologically, and allows the eyes of the entire community to perform an extra security audit as already happens in the world of open source software. In this paper, two RISC-V-based nodes are evaluated. Each node has the Kendryte K210 chip, which is the component based on this architecture. This paper describes the characteristics of the hardware, the tools to be used, the process of the environment preparation and the development on these devices and a discussion on their capabilities and ease of use.
Every day the IoT (and AIoT) market grows, and with this growing the impact of the technology in our lives gets bigger. From the phones in the pocket to the smart fridges, the connection of human daily life to internet is constantly expanding, with the benefits and risk that it takes within. These devices may work with open source software, so the user is totally aware of what is going on at a software level. However, the same cannot be said about the hardware unless the manufacturer decides to release the design. That’s where RISC-V comes in, an open ISA (Instruction Set Architecture). RISC-V is an open ISA. Unlike its competitors, the development of the chip does not start by paying (million dollar) licenses, it allows more innovation by being more accessible, both economically and technologically, and allows the eyes of the entire community to perform an extra security audit as already happens in the world of open source software. In this paper, two RISC-V-based nodes are evaluated. Each node has the Kendryte K210 chip, which is the component based on this architecture. This paper describes the characteristics of the hardware, the tools to be used, the process of the environment preparation and the development on these devices and a discussion on their capabilities and ease of use.
Description
Trabajo de Fin de Grado en Ingeniería Informática, Facultad de Informática UCM, Departamento de Arquitectura de Computadores y Automática, Curso 2020-2021. El código asociado está en el repositorio https://github.com/DalaiLamana/TFGDanielLamanaRISC-V licenciado bajo LGPL-3.0.