Publication: Implementación de una red en chip en un procesador RISC-V
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2022
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Abstract
Las redes en chip (NoC) son una tecnología emergente alternativa a los métodos de interconexión convencionales en la que se aplican los métodos de diseño de redes a las conexiones entre módulos. Permiten una mayor escalabilidad, abstracción, flexibilidad y resiliencia que las conexiones intra-chip convencionales.
Aunque las NoC han sido ampliamente usadas para la intra- comunicación entre procesadores y dispositivos complejos, en este Trabajo de Fin de Grado aplicamos esta metodología dentro de la unidad de ejecución de un procesador basado en la arquitectura libre RISC-V: el SWerv-EL2.
Por otro lado, en las FPGAs la reconfiguración dinámica posibilita añadir, sustituir y eliminar elementos heterogéneos en tiempo de ejecución, permitiéndonos incorporar funcionalidades conforme van siendo necesarias, o aportar redundancia y reemplazar módulos defectuosos para hacer nuestro diseño más tolerante a fallos.
Para ello, hemos estudiado a fondo y diseñado una NoC, tratando de minimizar los recursos consumidos y el impacto en área de la misma en el procesador. Posteriormente modificamos la unidad de ejecución del procesador para incluir dicha red como inter conexión entre los módulos de dicha unidad. En ambos casos usaremos el lenguaje de descripción de hardware SystemVerilog.
Finalmente se comentan los problemas encontrados durante el proyecto, los resultados y conclusiones, y el trabajo futuro posible para la continuación de este proyecto.
Network on a Chip (NoC) is an emergent technology alternative to traditional inter connection methods, in which network design methods are applied to the connexions between modules. They allow greater scalability, abstraction, flexibility and resilience than conventional on-chip networks. Although NoCs have been widely used to connect processors and complex devices, in this Final Degree Project, we apply this technology inside the execution unit of the RISC-V based processor SWerv-EL2. Secondly, using a dynamically partially reconfigurable FPGA permits adding, moving, replacing and removing heterogeneous elements at run-time, enabling us to insert fea tures as needed or to provide redundancy by replacing defective modules to make our design fault-tolerant. For this, we have studied in-depth and designed a NoC, trying to minimize the resources utilized and its impact on the core. Afterwards, we modified the execution unit of the core to include said network, using it to interconnect its submodules. In both cases, we used the hardware description language SystemVerilog. In the end, we discuss the problems encountered during the project, the results and conclusions, and possible future works.
Network on a Chip (NoC) is an emergent technology alternative to traditional inter connection methods, in which network design methods are applied to the connexions between modules. They allow greater scalability, abstraction, flexibility and resilience than conventional on-chip networks. Although NoCs have been widely used to connect processors and complex devices, in this Final Degree Project, we apply this technology inside the execution unit of the RISC-V based processor SWerv-EL2. Secondly, using a dynamically partially reconfigurable FPGA permits adding, moving, replacing and removing heterogeneous elements at run-time, enabling us to insert fea tures as needed or to provide redundancy by replacing defective modules to make our design fault-tolerant. For this, we have studied in-depth and designed a NoC, trying to minimize the resources utilized and its impact on the core. Afterwards, we modified the execution unit of the core to include said network, using it to interconnect its submodules. In both cases, we used the hardware description language SystemVerilog. In the end, we discuss the problems encountered during the project, the results and conclusions, and possible future works.
Description
Trabajo de Fin de Grado en Ingeniería Informática, Facultad de Informática UCM, Departamento de Arquitectura de Computadores y Automática, Curso 2021/2022.