Publication: Effect of interlayer trapping and detrapping on the determination of interface state densities on high-k dielectric stacks
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2009
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Al/HfO(2)/SiNx:H/n-Si metal-insulator-semiconductor (MIS) capacitors have been studied by electrical characterization. Films of silicon nitride were directly grown on n-type silicon substrates by electron-cyclotron-resonance assisted chemical-vapor-deposition (ECR-CVD). Silicon nitride thickness was varied from 2.96 to 6.64 nm. Afterwards, 12 nm thick hafnium oxide films were deposited by the high-pressure reactive sputtering (HPS) approach. Interface state densities were determined by deep-level transient spectroscopy and simultaneous high and low frequency capacitance-voltage (HLCV). The simultaneous measurements of the high and low frequency capacitance voltage provide interface trap density values in the range of 10(11) cm(2) eV(-1) for all the samples. However, a significant increase of this density of about two orders of magnitude was obtained by DLTS for the thinnest silicon nitride interfacial layers. In this work we probe that this increase is an artifact that must be attributed to traps existing at the HfO(2)/SiN(x):H interlayer interface. These traps are more easily charged or discharged as this interface comes near the substrate, that is, as thinner the SiN(x):H interface layer. The trapping/detrapping mechanisms increase the capacitance transient and, in consequence, the DLTS measurements have contributions not only from the insulator/substrate interface but also from the HfO(2)/SiN(x):H interlayer interface.
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Spanish Conference on Electron Devices (7.2009.Santiago de Compostela). © 2009 IEEE. The study was partially supported by the local government (Junta de Castilla y León) under Grant No. VAO 1 8A06, and by the Spanish TEC2007 under Grant No. 63318 and TEC2008 under Grant No. 06988-C02-02.
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