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González Rodríguez, Diego (2015) Aceleración de técnicas de ajuste de bloques mediante el procesador Nios II. [Thesis]
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| Item Type: | Thesis |
|---|---|
| Additional Information: | Tesis inédita de la Universidad Complutense de Madrid, Facultad de Informática, Departamento de Arquitectura de Computadores y Automática, leída el 16-09-2014 |
| Directors: | Directors Botella Juan, Guillermo |
| Uncontrolled Keywords: | Microprocesadores, fpga (hardware) |
| Palabras clave (otros idiomas): | Microprocessors, Field Programmable Gate Arrays |
| Subjects: | Sciences > Computer science > Hardware |
| ID Code: | 28240 |
| Deposited On: | 06 Feb 2015 14:48 |
| Last Modified: | 06 Feb 2015 14:48 |
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