A power-efficient and scalable load-store queue design



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Castro, F. and Chaver Martínez, Daniel Ángel and Piñuel Moreno, Luis and Prieto Matías, Manuel and Huang, M. C. and Tirado Fernández, Francisco (2005) A power-efficient and scalable load-store queue design. In Integrated circuit and system design: power and timing modeling, optimization and simulation. Springer-Verlag Berlin, pp. 1-9. ISBN 3-540-29013-3

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Official URL: http://link.springer.com/chapter/10.1007/11556930_1


The load-store queue (LQ-SQ) of modem superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the capacity requirements for the LQ-SQ increase, and its design becomes a challenge due to its CAM structure. In this paper we propose an efficient load-store queue state filtering mechanism that provides a significant energy reduction (on average 35% in the LSQ and 3.5% in the whole processor), and only incurs a negligible performance loss of less than 0.6%.

Item Type:Book Section
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© Springer-Verlag Berlin Heidelberg 2005.
We want to thank Simha Sethumadhavan for his helpful and thorough comments.
International Workshop on Power and Timing Modeling, Optimization and Simulation (15th. sep 21-23, 2005.Lovaina, Belgica).

Uncontrolled Keywords:Computer science, hardware & architecture; Computer science, theory & methods; Engineering, electrical & electronic
Subjects:Sciences > Computer science
Sciences > Computer science > Computer programming
ID Code:29749
Deposited On:11 May 2015 09:39
Last Modified:11 May 2015 09:39

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