Publication: A power-efficient and scalable load-store queue design
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2005
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Springer-Verlag Berlin
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Abstract
The load-store queue (LQ-SQ) of modem superscalar processors is responsible for keeping the order of memory operations. As the performance gap between processing speed and memory access becomes worse, the capacity requirements for the LQ-SQ increase, and its design becomes a challenge due to its CAM structure. In this paper we propose an efficient load-store queue state filtering mechanism that provides a significant energy reduction (on average 35% in the LSQ and 3.5% in the whole processor), and only incurs a negligible performance loss of less than 0.6%.
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© Springer-Verlag Berlin Heidelberg 2005.
We want to thank Simha Sethumadhavan for his helpful and thorough comments.
International Workshop on Power and Timing Modeling, Optimization and Simulation (15th. sep 21-23, 2005.Lovaina, Belgica).
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