Publication: Filtro adaptativo tolerante a fallos
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2014
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Abstract
Los detectores de partículas (como el conformador trapezoidal utilizado en este proyecto) son utilizados en una gran variedad de aplicaciones (aceleradores de partículas, satélites artificiales,…). Esta clase de sistemas contienen diversos tipos de filtros digitales y uno de los más ampliamente utilizados es el conformador trapezoidal. Debido a su campo de aplicación, esta clase de sistemas están sometidos a grandes dosis de radiación que pueden llegar a producir daños en el sustrato físico sobre el que se ha diseñado los circuitos y consecuentemente producir fallos en el funcionamiento de dicho circuito. Este proyecto consiste en implementar este tipo de conformador sobre una FPGA Virtex-6 y dotarle de tolerancia a fallos utilizando la capacidad de reconfiguración dinámica parcial que posee esta familia de FPGAs. Así, se rediseñará el filtro para que sea posible cambiar la ubicación de sus componentes en tiempo de ejecución cuando se detecte un daño en el sustrato físico de la FPGA sobre el que está ubicado. Al reubicar dicho componente en una región de la FPGA libre de daños conseguiremos que el dispositivo pueda seguir operando tras la aparición y detección del fallo.
En el proyecto se han abordado tres tareas:
1. Por un lado el diseño del conformador trapezoidal clásico siguiendo la descripción proporcionada por su creador. Se ha verificado su funcionamiento mediante simulación funcional y se ha sintetizado para medir los recursos de la FPGA que requiere.
2. A continuación se ha rediseñado el conformador para que sea posible cambiar la ubicación física de sus componentes y que siga funcionando correctamente, dotándole de esta forma de tolerancia a fallos. La ubicación de los componentes es una característica física del diseño, pero que sea posible cambiarla en tiempo de ejecución sin afectar a la funcionalidad del diseño requiere adaptaciones a nivel lógico. Ello nos obligó a rediseñar el conformador: generar un bus común para las comunicaciones entre los módulos, el diseño de un árbitro de bus y los correspondientes esclavos y el rediseño de los componentes iniciales del filtro para adaptarse a su nueva estructura. Se ha verificado su funcionamiento mediante simulación funcional y se ha sintetizado para medir los recursos de la FPGA que requiere.
3. Finalmente, se utilizó la herramienta PlanAhead para crear distintas configuraciones del diseño, cada una de las cuales es una reconfiguración parcial del mismo. Para ello se implementó una parte estática gracias a la cual los dispositivos dinámicos (susceptibles a cambios en la configuración) pudiesen comunicarse entre ellos. Esta parte estática se implementó como una topología de comunicación que utilizaba dos buses, y contiene el árbitro de bus y los esclavos que hacen de interfaces con los dispositivos dinámicos. De nuevo, se ha verificado el funcionamiento de cada configuración mediante simulación, pero en este caso la simulación es post Place&Route para tener que simular cualquier modificación causada por la distinta ubicación y rutado de los módulos dentro de la FPGA.
Particle detectors (such as trapezoidal shaper used for this project) are used in a variety of applications (particle accelerators, artificial satellites...). Such systems include various types of digital filters and one of the most widely used, is the trapezoidal shaper. Due to its scope, such systems are subjected to large doses of radiation that can produce damage to the physical substrate on which the circuit is designed and consequently produce malfunction of the circuit. This project is to implement this type of shaper on a Virtex-6 FPGA and provide it with fault tolerance using partial dynamic reconfiguration capability possessed by this family of FPGAs. Thus, it will provide the ability to filter some of its components can be relocated when a fault is detected in the physical substrate of the FPGA, so that the device can continue to operate after the occurrence and failure detection. So, will redesign the filter to be able to change the location of its components at run time when damage to the physical substrate of the FPGA on which it is located is detected. By relocating the component in a region of the FPGA harmless get the device to continue operating after the occurrence and failure detection. The project has addressed three tasks: 1. On one hand the trapezoidal shaping classic design following the description provided by its creator. Operation has been verified by functional simulation and synthesized to measure the FPGA resources required. 2. Then the shaper was redesign to provide it with fault tolerance. This forced to redesign of the design: creating a common bus for communication between modules, the design of a bus master and slave and the corresponding initial redesign of filter components to suit its new structure. Operation has been verified by functional simulation and synthesized to measure the FPGA resources required. 3. Finally, the tool to create PlanAhead different design configurations, each of which is a partial reconfiguration of the same is used. To do a static part through which the dynamic devices (susceptible to configuration changes) could communicate with them was implemented. This static part is implemented as a communication topology used two buses, and contains the bus arbiter and slaves that make as an interface for the dynamic devices. Again, it has been verified to work each configuration by simulation, but in this case the simulation is Place & Route port to have to pretend any changes caused by the different location and routing modules within the FPGA.
Particle detectors (such as trapezoidal shaper used for this project) are used in a variety of applications (particle accelerators, artificial satellites...). Such systems include various types of digital filters and one of the most widely used, is the trapezoidal shaper. Due to its scope, such systems are subjected to large doses of radiation that can produce damage to the physical substrate on which the circuit is designed and consequently produce malfunction of the circuit. This project is to implement this type of shaper on a Virtex-6 FPGA and provide it with fault tolerance using partial dynamic reconfiguration capability possessed by this family of FPGAs. Thus, it will provide the ability to filter some of its components can be relocated when a fault is detected in the physical substrate of the FPGA, so that the device can continue to operate after the occurrence and failure detection. So, will redesign the filter to be able to change the location of its components at run time when damage to the physical substrate of the FPGA on which it is located is detected. By relocating the component in a region of the FPGA harmless get the device to continue operating after the occurrence and failure detection. The project has addressed three tasks: 1. On one hand the trapezoidal shaping classic design following the description provided by its creator. Operation has been verified by functional simulation and synthesized to measure the FPGA resources required. 2. Then the shaper was redesign to provide it with fault tolerance. This forced to redesign of the design: creating a common bus for communication between modules, the design of a bus master and slave and the corresponding initial redesign of filter components to suit its new structure. Operation has been verified by functional simulation and synthesized to measure the FPGA resources required. 3. Finally, the tool to create PlanAhead different design configurations, each of which is a partial reconfiguration of the same is used. To do a static part through which the dynamic devices (susceptible to configuration changes) could communicate with them was implemented. This static part is implemented as a communication topology used two buses, and contains the bus arbiter and slaves that make as an interface for the dynamic devices. Again, it has been verified to work each configuration by simulation, but in this case the simulation is Place & Route port to have to pretend any changes caused by the different location and routing modules within the FPGA.
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Trabajo de Fin de Grado en Ingeniería Informática (Universidad Complutense, Facultad de Informática, curso 2013/2014)