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Write-aware replacement policies for PCM-based systems



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Rodríguez, Rodríguez and Castro Rodríguez, Fernando and Chaver, D. and González Alberquilla, R. and Piñuel Moreno, Luis and Tirado Fernández, Francisco (2015) Write-aware replacement policies for PCM-based systems. Computer journal, 58 (9). pp. 2000-2025. ISSN 0010-4620

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Official URL: http://dx.doi.org/10.1093/comjnl/bxu104


The gap between processor and memory speeds is one of the greatest challenges that current designers face in order to develop more powerful computer systems. In addition, the scalability of the Dynamic Random Access Memory (DRAM) technology is very limited nowadays, leading one to consider new memory technologies as candidates for the replacement of conventional DRAM. Phase-Change Memory (PCM) is currently postulated as the prime contender due to its higher scalability and lower leakage. However, compared with DRAM, PCM also exhibits some drawbacks, like lower endurance or higher dynamic energy consumption and write latency, that need to be mitigated before it can be used as the main memory technology for the next generation of computers. This work addresses the PCM endurance constraint. For this purpose, we present an analysis of conventional cache replacement policies in terms of the amount of writebacks to main memory that they imply and we also propose some new replacement algorithms for the last-level cache (LLC) with the goal of cutting down the write traffic to memory and consequently, to increase PCM lifetime without degrading system performance. In this paper, we target general purpose processors provided with this kind of non-volatile main memory and we exhaustively evaluate our proposed policies in both single- and multi-core environments. Experimental results show that, on average, compared with a conventional Least Recently Used (LRU) algorithm, some of our proposals manage to reduce the amount of writes to main memory up to 20-30% depending on the scenario evaluated, which leads to memory endurance extensions of up to 20-45%, also reducing the energy consumption in the memory hierarchy by up to 9% and hardly degrading performance.

Item Type:Article
Additional Information:

This work has been supported in part by the Spanish government through the research contract CICYT-TIN 2008/508, TIN2012-32180 and the HIPEAC-3 European Network of Excellence. Also it was supported by a grant scholarship from the University of Costa Rica and Costa Rican Ministry of Science and Technology MICIT and CONICIT.

Uncontrolled Keywords:High-performance; Main memory; Technology; Algorithms; Caches
Subjects:Sciences > Computer science > Computer programming
ID Code:34375
Deposited On:24 Nov 2015 18:36
Last Modified:15 Dec 2015 11:43

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