Publication:
A low cost matching motion estimation sensor based on the NIOS II microprocessor.

Loading...
Thumbnail Image
Full text at PDC
Publication Date
2012-10
Authors
González, Diego
Meyer Baese, Uwe
Sanz, Concepción
Tirado Fernández, Francisco
Advisors (or tutors)
Editors
Journal Title
Journal ISSN
Volume Title
Publisher
MDPI AG
Citations
Google Scholar
Research Projects
Organizational Units
Journal Issue
Abstract
Medical imaging has become an absolutely essential diagnostic tool for clinical practices; at present, pathologies can be detected with an earliness never before known. Its use has not only been relegated to the field of radiology but also, increasingly, to computer-based imaging processes prior to surgery. Motion analysis, in particular, plays an important role in analyzing activities or behaviors of live objects in medicine. This short paper presents several low-cost hardware implementation approaches for the new generation of tablets and/or smartphones for estimating motion compensation and segmentation in medical images. These systems have been optimized for breast cancer diagnosis using magnetic resonance imaging technology with several advantages over traditional X-ray mammography, for example, obtaining patient information during a short period. This paper also addresses the challenge of offering a medical tool that runs on widespread portable devices, both on tablets and/or smartphones to aid in patient diagnostics.
Description
© 2012 by the authors. The authors would like to thank Altera for providing hardware and software under the University programs. This work was partially supported by Spanish research projects, TIN 2008-00508 and TIN 2012-32180.
Unesco subjects
Keywords
Citation
1. CCITT SGXV. Working Party XV/4, Specialists Group on Coding for Visual Telephony. Description of Reference Model 8 (RM8); Document 525; 1989. 2. ITU Telecommunication Standardization Sector LBC-95, Study Group 15, Working Party 15/1. Expert’s Group on Very Low Bitrate Visual Telephony, from Digital Video Coding Group, Telenor Research and Development; 1995. 3. ISO/IEC CD 11172-2 (MPEG-1 Video). Information Technology—Coding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1.5 Mbits/s: Video; 1993. 4. ISO/IEC CD 13818-2–ITU-T H.262 (MPEG-2 Video). Information Technology—Generic Coding of Moving Pictures and Associated Audio Information: Video; 1995. 5. Marpe, D.; Wiegand, T.; Sullivan, G.J. The H.264/MPEG4 advanced video coding standard and its applications. IEEE Commun. Mag. 2006, 44, 134–143. 6. ITU-T Recommendation H.264 (draft). International standard for advanced video coding; 2003. 7. ITU-T Recommendation H.264 & ISO/IEC 14496-10 (MPEG-4) AVC. Advance Video Coding for Generic Audiovisual Services; 2005. 8. Botella, G.; Garcia, A.; Rodriguez-Alvarez, M.; Ros, E.; Meyer-Baese, U.; Molina, M.C. Robust bioinspired architecture for optical-flow computer. IEEE Trans. VLSI Syst. 2010, 18, 616–629. 9. Botella, G.; Meyer-Baese, U.; Garcia, A. Bio-inspired robust optical flow processor system for VLSI implementation. Electron. Lett. 2009, 45, 1304–1305. 10. Deutschmann, R.; Koch, C. An Analog VLSI Velocity Sensor Using the Gradient Method. In Proceedings of the IEEE International Symposium on Circuits and Systems, Monterey, CA, USA, 31 May1998. 11. Stocker, A.-A.; Douglas, R.-J. Analog Integrated 2D Optical Flow Sensor with Programmable Pixels. In Proceedings of the IEEE International Symposium on Circuits and Systems, Vancouver, BC, USA, 23 May 2004. 12. Stocker, A.-A. Analog Integrated 2D Optical Flow Sensor. In Analog Integrated Circuits and Signal Processing; Springer: New York, NY, USA, 2006; Volume 42, pp. 121–138. 13. Horn, B.; Schunck, B. Determining optical flow. Artif. Intell. 1981, 17, 185–213. 14. Niitsuma, H.; Maruyama, T. Real-Time Detection of Moving Objects. In Proceedings of the IEEE International Conference on Field Programmable Logic and Applications, Leuven, Belgium, 30 August 2004; pp. 1153–1157. 15. Im, Y.L.; Il-Hyun, P.; Dong-Wook, L.; Ki-Young, C. Implementation of the H.264/AVC Decoder Using the Nios II Processor. Available online: http://www.altera.com/literature/dc/ 1.5-2005_Korea_2nd_SeoulNational-web.pdf (accessed on 14 August 2012). 16. Anafocus. Anafocus Leading on-chip vision solutions. Available online: http://www.anafocus.com (accessed on 23 July 2012). 17. Konrad, J. Estimating motion in image sequences. IEEE Signal Process Mag. 1999, 16, 70-91. 18. Altera. Nios II C-to-Hardware Acceleration Compiler. Available online: http://www.altera.com/ devices/processor/nios2/tools/c2h/ni2-c2h.html (accessed on 22 June 2012). 19. Altera. Altera. Available online: http://www.altera.com (accessed on 15 May 2012). 20. Sohm, O.P. Fast DCT algorithm for DSP with VLIW architecture. U.S. Patent 20,070,078,921, 5 April 2007. 21. Kappagantula, S.; Rao, K.-R. Motion compensated interframes image prediction. IEEE Trans. Commun. 1985, 33, 1011–1015. 22. Kuo, C.-J.; Yeh, C.-H.; Odeh, S.-F. Polynomial Search Algorithms for Motion Estimation. In Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, Orlando, FL, USA, 11 July 2012; pp. 813–818. 23. Zhu, S.; Ma, K.-K. A new diamond search algorithm for fast block-matching motion estimation. IEEE Trans. Image Process. 2000, 9, 287–290. 24. Zhu, S. Fast Motion Estimation Algorithms for Video Coding. M.S. thesis, Nanyang Technology University: Singapore, 1998. 25. Koga, T.; Iinuma, K.; Hirano, A.; Iijima, Y.; Ishiguro, T. Motion-Compensated Interframe Coding for Video Conferencing. In Proceedings of the IEEE National Telecommunications Conference, New Orleans, LA, USA, 15 November 1981. 26. Liu, B.; Zaccarin, A. New fast algorithms for estimation of block motion vectors. IEEE Trans. Circuit. Syst. Video Technol. 1993, 3, 148–157. 27. Li, R.; Zeng, B.; Liou, M.-L. A new three-step search algorithm for block motion estimation. IEEE Trans. Circuit. Syst. Video Technol. 1994, 4, 438–422. 28. Po, L.-M.; Ma, W.-C. A novel four-step search algorithm for fast block motion estimation. IEEE Trans. Circuit. Syst. Video Technol. 1996, 6, 313–317. 29. Liu, L.-K.; Feig, E. A block-based gradient descent algorithm for fast block motion estimation in video coding. IEEE Trans. Circuit. Syst. Video Technol. 1996, 6, 419–422. 30. Jain, J.-R.; Jain, A.-K. Displacement measurement and its application in interframes image coding. IEEE Trans. Commun. 1981, 29, 1799–1808. 31. Ghanbari, M. The cross-search algorithm for motion estimation. IEEE Trans. Commun. 1990, 38, 950–953. 32. Lee, L.-W.; Wang, J.-F.; Lee, J.-Y.; Shie, J.-D. Dynamic search-window adjustment and interlaced search for block-matching algorithm. IEEE Trans. Circuit. Syst. Video Technol. 1993, 3, 85–87. 33. Zhu, C.; Lin, X.; Chau, L.-P. Hexagon_based search pattern for fast block motion estimation. IEEE Trans. Circuit. Syst. Video Technol. 2002, 12, 349–355. 34. Tham, J.-Y.; Ranganath, S.; Ranganath, M.; Kassim, A.-A. A novel unrestricted center-biased diamond search algorithm for block motion estimation. IEEE Trans. Circuit. Syst. Video Technol. 1998, 8, 369–377. 35. Li, Y.; Xu, L.Q.; Morrison, D.; Nightingale, C.; Morphett, J. Method and System for Estimating Global Motion in Video Sequences. U.S. Patent 200,600,722,003, 6 April 2006. 36. Monro, D.-M. Matching Pursuits Basis Selection Design. U.S. Patent 200,800,849,240, 10 April 2008. 37. Bei, C.-D.; Gray, R.-M. An improvement of the minimum distortion encoding algorithm for vector quantization. IEEE Trans. Commun. 1985, 33, 1132–1133. 38. Montrucchio, B.; Quaglia, D. New sorting-based lossless motion estimation algorithms and a partial distortion elimination performance analysis. IEEE Trans. Circuit. Syst. Video Technol. 2005, 15, 210–220. 39. Cheung, C.-K.; Po, L.-M. Normalized partial distortion search algorithm for block motion estimation. IEEE Trans. Circuit. Syst. Video Technol. 2000, 10, 417–422. 40. Cheung, C.-K.; Po, L.-M. Adjustable partial distortion search algorithm for fast block motion estimation. IEEE Trans. Circuit. Syst. Video Technol. 2003, 13, 100–110. 41. Jain, J.-R.; Jain, A.-K. Displacement measurement and its application in interframes image coding. IEEE Trans. Commun. 1981, 29, 1799–1808. 42. Chu, P. Embedded SoPC Design with NIOS II Processor and Examples; Wiley: Hoboken, NJ, USA, 2012. 43. Altera. FPGAs. Available online: http://www.altera.com/products/fpga.html (accessed on 29 June 2012). 44. Xilinx. Field Programable Gate Array (FPGA). Available online: http://www.xilinx.com/ training/fpga/fpga-field-programmable-gate-array.htm (accessed on 29 June 2012). 45. Ashenden, P.J. VHDL standards. IEEE Des. Test Comput. 2001, 18, 122–123. 46. Hamblen, J.O.; Hall, T.S.; Furman, M.D. Rapid Prototyping of Digital Systems, 2nd ed.; Springer: Atlanta, GA, USA, 2009. 47. Botella, G.; González, D. Real-Time Motion Processing Estimation Methods in Embedded Systems. In Real-Time Systems, Architecture, Scheduling, and Application; Intech Publishing: New York, NY, USA, 2012; Chapter 13, pp. 265–292. 48. Altera. Nios II Performance Benchmarks. Available online: http://www.altera.com/literature/ ds/ds_nios2_perf.pdf (accessed on 26 June 2012). 49. Altera. Documentation: Nios Processor. Available online: http://www.altera.com/literature/ lit-nio.jsp (accessed on 3 June 2012). 50. Altera. Webpage Stratix II FPGA: High Performance with Great Signal Integrity. Available online: http://www.altera.com/devices/fpga/stratix-fpgas/stratix-ii/stratix-ii/st2-index.jsp (accessed on 6 July 2012). 51. Arm. ARM The architecture for the Digital World. Available online: http://www.arm.com/ products/processors/classic/arm9/ (accessed on 18 August 2012). 52. Altera. Cyclone II FPGAs at Cost That Rivals ASICs. Available online: http://www.altera.com/ devices/fpga/cyclone2/ cy2-index.jsp (accessed on 15 May 2012). 53. Altera. Avalon Interface Specifications. Available online: http://www.altera.com/literature/ manual/mnl_avalon_spec.pdf (accessed on 15 July 2012). 54. Yushin, C. CIPR Sequences. Available online: http://www.cipr.rpi.edu/resource/sequences/ (accessed on 10 June 2012). 55. Guzmán, P.; Díaz, J.; Agís, R.; Ros, E. Optical flow in a smart sensor based on hybrid analog-digital architecture. IEEE Sens. J. 2010, 10, 2975–2994. 56. Baker, S.; Matthews, I. Lucas-Kanade 20 years on: A unifying framework. Int. J. Comput. Vis. 2004, 56, 221–255. 57. Xilinx. Datasheet XC2V6000-5FF1152I-Virtex-II 1.5V Field-Programmable Gate Arrays-Xilinx, Inc. Available online: http://www.alldatasheet.com/datasheet-pdf/pdf/97992/XILINX/ XC2V6000-5FF1152I.html (accessed on 18 August 2012).
Collections