Publication:
Evaluating the SEE sensitivity of a 45nm SOI Multi-core Processor due to 14 MeV Neutrons

Research Projects
Organizational Units
Journal Issue
Abstract
The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric Multi-Processing mode running a memory-bound application, whereas the second one uses the Symmetric Multi-Processsing mode running a CPU-bound application. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the Freescale P2041 multi-core manufactured in 45nm SOI technology. A deep analysis of the observed errors in cache memories was carried-out in order to reveal vulnerabilities in the cache protection mechanisms. Critical zones like tag addresses were affected during the experiments. In addition, the results show that the sensitivity strongly depends on the application and the multi-processsing mode used.
Description
“© © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.”
Keywords
Citation
[1] R. Hyman, K. Bhattacharya, and N. Ranganathan, “Redundancy Mining for Soft Error Detection in Multicore Processors,” IEEE Trans. Comp., vol. 60, pp. 1114–1125, Aug. 2011. [2] F. Certification Authorities Software Team (CAST) , “Position paper cast-32 multi-core processors.” [Online]. Available: https://www.faa.gov/aircraft/air_cert/design_approvals/air_software/ cast/cast_papers/media/cast-32.pdf, May. 2014. [3] C. Villalpando, D. Rennels, R. Some, and M. Cabanas-Holmen, “Re- liable Multicore Processors for NASA Space Missions,” in Proc. Aerospace Conference, pp. 1–12, Mar. 2011. [4] P.E. Dodd and L.W. Massengill, “Basic mechanisms and modeling of single-event upset in digital microelectronics,” IEEE Trans. Nucl. Sci., vol. 50, pp. 583–602, June 2003. [5] G.Gasiot,V.Ferlet-Cavrois,J.Baggio,P.Roche,P.Flatresse,A.Guyot, P. Morel, O. Bersillon, and J. du Port de Pontcharra, “SEU Sensitivity of Bulk and SOI Technologies to 14-MeV Neutrons,” IEEE Trans. Nucl. Sci., vol. 49, pp. 3032–3037, Dec. 2002. [6] Asadi, G.H. and Vilas, S. and Tahoori, M.B. and Kaeli, D., “Balancing performance and reliability in the memory hierarchy,” in Proc. Perfor- mance Analysis of Systems and Software, pp. 269–279, Mar. 2005. [7] P. Ramos, V. Vargas, M. Baylac, F. Villa, S. Rey, J.A. Clemente, N.E. Zergainoh, and R. Velazco, “Sensitivity to Neutron Radiation of a 45nm SOI Multi-core Processor,” in Proc. Radiation Effects on Components and Systems, pp. 1–4, Sep. 2015. [8] E. Normand and L. Dominik, “Cross Comparison Guide for Results of Neutron SEE Testing of Microelectronics Applicable to Avionics,” in Proc. Radiation Effects Data Workshop, pp. 1–8, July 2010. [9] S.S. Stolt and E. Normand, “A Multicore Server SEE Cross Section Model,” IEEE Trans. Nucl. Sci., vol. 59, pp. 2803–2810, Dec. 2012. [10] D.A.G. Oliveira, P. Rech, H.M. Quinn, T.D. Fairbanks, L. Monroe, S.E. Michalak, C. Anderson-Cook, P.O.A. Navaux, and L. Carro, “Mod- ern GPUs Radiation Sensitivity Evaluation and Mitigation Through Du- plication With Comparison,” IEEE Trans. Nucl. Sci., vol. 61, pp. 3115– 3122, Dec. 2014. [11] M. Rebaudengo, M. Reorda, and M. Violante, “An accurate analysis of the effects of soft errors in the instruction and data caches of a pipelined microprocessor,” in Proc. Design, Automation and Test in Europe Conference and Exhibition, pp. 602–607, 2003. [12] T. Santini, P. Rech, G. Nazar, L. Carro, and F. Rech Wagner, “Reducing Embedded Software Radiation-Induced Failures Through Cache Memo- ries,” in Proc. European Test Symposium, pp. 1–6, May 2014. [13] QNX Software Systems, “Running AMP, SMP or BMP Mode for Mul- ticore Embedded Systems.” [Online]. Available: http://cache.freescale. com/files/32bit/doc/brochure/PWRARBYNDBITSRAS.pdf, 2012. [14] F. Villa, M. Baylac, S. Rey, O. Rossetto, W. Mansour, P. Ramos, R. Velazco, and G. Hubert, “Accelerator-Based Neutron Irradiation of Integrated Circuits at GENEPI2 (France),” in Proc. Radiation Effects Data Workshop, pp. 1–5, July 2014. [15] F. Miller, C. Weulersse, T. Carriere, N. Guibbaud, S. Morand, and R. Gaillard, “Investigation of 14 MeV Neutron Capabilities for SEU Hardness Evaluation,” IEEE Trans. Nucl. Sci., vol. 60, pp. 2789–2796, Aug. 2013. [16] Freescale, “P2040/P2041 QorIQ Integrated Multicore Communication Processor Family Reference Manual.” [Online]. Available: http://www. freescale.com/webapp/sps/site/prod_summary.jsp?code=P2040, 2013. [17] Freescale,“e500mcCoreReferenceManual.”[Online].Available:http:// cache.freescale.com/files/32bit/doc/ref_manual/E500MCRM.pdf, 2013. [18] E. Francesquini, M. Castro, P. Penna, F. Dupros, H. Freitas, P. Navaux, and J.F. Mehaut, “On the energy efficiency and performance of irregular application executions on multicore, NUMA and manycore platforms,” Journal of Parallel and Distributed Computing, vol. 76, pp. 32–48, Feb. 2015. [19] J. Autran, P. Munteanu, P. Roche, and G. Gasiot, “Real-time Soft- Error Rate Measurements: A Review,” Microelectronics Reliability, vol. 54, pp. 1455–1476, Feb. 2014. [20] R. Velazco, J.A. Clemente, G. Hubert, W. Mansour, C. Palomar, F.J. Franco, M. Baylac, S. Rey, O. Rosetto, and F. Villa, “Evidence of the Robustness of a COTS Soft-Error Free SRAM to Neutron Radiation,” IEEE Trans. Nucl. Sci., vol. 61, pp. 3103–3108, Dec. 2014. [21] N. De Witte, R. Vincke, S. Van Landschoot, E. Steegmans, and J. Boydens, “Comparing Dual-Core SMP/AMP Performance on a Telecom Architecture.” [Online]. Available:https://lirias.kuleuven.be/ bitstream/123456789/416618/1/072_Paper-N_Witte.pdf, Dec. 2013.
Collections