Janus: an FPGA-based system for high-performance scientific computing



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Fernández Pérez, Luis Antonio and Martín Mayor, Víctor and Muñoz Sudupe, Antonio and Yllanes, D. and otros, ... (2009) Janus: an FPGA-based system for high-performance scientific computing. Computing in science & engineering, 11 (1). pp. 48-58. ISSN 1521-9615

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Official URL: http://dx.doi.org/10.1109/mcse.2009.11


This paper describes JANUS, a modular massively parallel and reconfigurable FPGA-based computing system. Each JANUS module has a computational core and a host. The computational core is a 4x4 array of FPGA-based processing elements with nearest-neighbor data links. Processors are also directly connected to an I/O node attached to the JANUS host, a conventional PC. JANUS is tailored for, but not limited to, the requirements of a class of hard scientific applications characterized by regular code structure, unconventional data manipulation instructions and not too large data-base size. We discuss the architecture of this configurable machine, and focus on its use on Monte Carlo simulations of statistical mechanics. On this class of application JANUS achieves impressive performances: in some cases one JANUS processing element outperfoms high-end PCs by a factor ≈1000. We also discuss the role of JANUS on other classes of scientific applications.

Item Type:Article
Additional Information:

© 2009, IEEE. Artículo firmado por 23 autores. We thank M. Lena and S. Sialino for their outstanding support during the commissioning of the first JANUS system.

Uncontrolled Keywords:Impurities; Ianus.
Subjects:Sciences > Physics
Sciences > Physics > Physics-Mathematical models
ID Code:37938
Deposited On:07 Jun 2016 09:40
Last Modified:07 Jun 2016 09:40

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