A Methodology to Emulate Single Event Upsets in Flip-Flops using FPGAs through Partial Reconfiguration and Instrumentation



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Serrano, Felipe and Clemente Barreira, Juan Antonio and Mecha López, Hortensia (2015) A Methodology to Emulate Single Event Upsets in Flip-Flops using FPGAs through Partial Reconfiguration and Instrumentation. IEEE Transactions on Nuclear Science, 62 (4). pp. 1617-1624. ISSN 0018-9499

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Official URL: http://ieeexplore.ieee.org/document/7181741/


This paper presents a methodology to emulate Single Event Upsets (SEUs) in FPGA flip-flops (FFs). Since the content of a FF is not modifiable through the FPGA configuration memory bits, a dedicated design is required for fault injection in the FFs. The method proposed in this paper is a hybrid approach that combines FPGA partial reconfiguration and extra logic added to the circuit under test, without modifying its operation. This approach has been integrated into a fault-injection platform, named NESSY (Non intrusive ErrorS injection SYstem), developed by our research group. Finally, this paper includes results on a Virtex-5 FPGA demonstrating the validity of the method on the ITC’99 benchmark set and a Feed-Forward Equalization (FFE) filter. In comparison with other approaches in the literature, this methodology reduces the resource consumption introduced to carry out the fault injection in FFs, at the cost of adding very little time overhead (1.6 �μs per fault).

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Uncontrolled Keywords:Single event upset (SEU), Fault injection, Flip-flops, FPGA, Reliability
Subjects:Sciences > Computer science > Hardware
ID Code:39054
Deposited On:08 Sep 2016 10:54
Last Modified:19 Sep 2016 10:19

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