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Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA

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Olivito, Javier and Serrano, Felipe and Clemente Barreira, Juan Antonio and Mecha, Hortensia and Resano, Javier (2018) Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA. IET Computers & Digital Techniques . pp. 1-33. ISSN 1751-8601 (In Press)

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Official URL: http://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2016.0095



Abstract

In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. We have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead.


Item Type:Article
Subjects:Sciences > Computer science > Integrated circuits
Sciences > Computer science > Hardware
Sciences > Computer science > Electronics
ID Code:46629
Deposited On:02 Mar 2018 09:43
Last Modified:28 May 2020 07:04

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