Publication: Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 FPGA
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Publication Date
2018-01-16
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Institution of Engineering and Technology
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Abstract
In this paper we have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. Our analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. We have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead.