Publication: Optimización de justicia y rendimiento en procesadores multicore asimétricos mediante planificación consciente de la contención
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2018
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Abstract
Los procesadores multicore asimétricos (AMPs) con repertorio común de instrucciones constituyen una alternativa de mayor eficiencia energética que los multicores simétricos para cargas de trabajo diversas. Los AMPs integran cores rápidos de alto rendimiento, con otros más lentos y de bajo consumo. Se ha demostrado que la planificación a nivel de sistema operativo y consciente de la asimetría es esencial para obtener beneficios significativos en cuanto a rendimiento global y para garantizar justicia en este tipo de sistemas. No obstante, para poder llevar esto a cabo, el planificador ha de estimar de forma precisa el progreso que cada hilo realiza al ejecutarse en los diversos tipos de core durante la ejecución. A pesar de la existencia de planificadores que optimizan la justicia o el rendimiento en AMPs, las propuestas existentes habitualmente dependen de extensiones hardware especiales o de modelos de predicción específicos de plataforma y, además, no tienen en cuenta la degradación del rendimiento asociada a la contención en los recursos compartidos (p.ej., caché compartida o bus de memoria). Esto puede limitar la portabilidad del planificador y producir una degradación significativa de la justicia y del rendimiento global. En este Trabajo de Fin de Máster se ha procedido al diseño e implementación en el kernel Linux de un planificador consciente de la contención en recursos compartidos en AMPs, que está orientado a la optimización de la justicia. Asimismo, el planificador expone un parámetro de configuración que permite mejorar gradualmente el rendimiento global a costa de degradar la justicia. La evaluación experimental del planificador propuesto se ha llevado a cabo utilizando hardware multicore asimétrico real.
Single-ISA Asymmetric Multicore Processors (AMPs) constitute a more energy efficient design approach than symmetric multicores for a wider variety of workloads. AMPs combine on the same chip high-performance big cores with energyefficient small ones. Previous research has highlighted that asymmetry-aware OS scheduling is paramount when it comes to ensuring fairness while delivering acceptable throughput on AMP systems. Nonetheless, to accomplish this the scheduler must accurately track the progress made by each thread while running on different core types throughout the execution. Despite the fact that some schedulers that seek to optimize fairness or throughput on AMPs have been proposed, these proposals usually rely on special hardware extensions or platform-specific estimation models to function, and, more importantly, they do not take into account the performance degradation that comes from shared-resource contention (e.g. due to shared caches/buses). This may limit the scheduler portability and may also lead to significant throughput/fairness degradation. The goal of this Master Thesis is to overcome these issues by designing and implementing an OS-level fairness-oriented scheduler that is aware of shared resource contention on AMPs. Notably, our scheduling proposal also exposes a configurable parameter making it possible to deliver a configurable trade-off between fairness and throughput. The experimental evaluation of our scheme has been conducted on real asymmetric hardware.
Single-ISA Asymmetric Multicore Processors (AMPs) constitute a more energy efficient design approach than symmetric multicores for a wider variety of workloads. AMPs combine on the same chip high-performance big cores with energyefficient small ones. Previous research has highlighted that asymmetry-aware OS scheduling is paramount when it comes to ensuring fairness while delivering acceptable throughput on AMP systems. Nonetheless, to accomplish this the scheduler must accurately track the progress made by each thread while running on different core types throughout the execution. Despite the fact that some schedulers that seek to optimize fairness or throughput on AMPs have been proposed, these proposals usually rely on special hardware extensions or platform-specific estimation models to function, and, more importantly, they do not take into account the performance degradation that comes from shared-resource contention (e.g. due to shared caches/buses). This may limit the scheduler portability and may also lead to significant throughput/fairness degradation. The goal of this Master Thesis is to overcome these issues by designing and implementing an OS-level fairness-oriented scheduler that is aware of shared resource contention on AMPs. Notably, our scheduling proposal also exposes a configurable parameter making it possible to deliver a configurable trade-off between fairness and throughput. The experimental evaluation of our scheme has been conducted on real asymmetric hardware.
Description
Máster en Ingeniería Informática, Facultad de Informática, Departamento de Arquitectura de Computadores y Automática, curso 2017-2018