Reconfigurable implementation of GF(2^m) bit-parallel multipliers



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Imaña Pascual, José Luis (2018) Reconfigurable implementation of GF(2^m) bit-parallel multipliers. In Proceedings of the 2018 Design, Automation and Test In Europe Conference and Exhibition (DATE). Design Automation and Test in Europe Conference and Exhibition . IEEE, Dresde, pp. 893-896. ISBN 978-3-9819-2630-9

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Hardware implementations of arithmetic operations over binary finite fields GF(2^m) are widely used in several important applications, such as cryptography, digital signal processing and error-control codes. In this paper, efficient. reconfigurable implementations of bit-parallel canonical basis multipliers over binary fields generated by type II irreducible pentanomials f_(y) = y^m + y^(n+2) + y^(n+1) + y^n + 1 are presented. These pentanomials are important because all five binary fields recommended by NIST for ECDSA can be constructed using such polynomials. In this work, a new approach for CF(2^m) multiplication based on type II pentanomials is given and several post-place and route implementation results in Xilinx Artix-7 FPGA are reported. Experimental results show that the proposed multiplier implementations improve the area x time parameter when compared with similar multipliers found in the literature.

Item Type:Book Section
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© 2018 IEEE
ISSN 1558-1101
Design, Automation and Test in Europe Conference and Exhibition (DATE) (2018. Dresde, Alemania)
Issn: 1530-1591
This work has been supported by the EU (FEDER) and the Spanish MINECO, under grants TIN 2015-65277-R and TIN2012-32180.

Uncontrolled Keywords:Pentanomials
Subjects:Sciences > Computer science > Artificial intelligence
ID Code:55397
Deposited On:28 May 2019 18:45
Last Modified:28 May 2019 18:55

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