LFSR-based bit-serial GF(^2m) multipliers using irreducible trinomials



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Imaña Pascual, José Luis (2021) LFSR-based bit-serial GF(^2m) multipliers using irreducible trinomials. IEEE transactions on computers, 70 (1). pp. 156-162. ISSN 0018-9340

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Official URL: http://dx.doi.org/10.1109/TC.2020.2980259


In this article, a new architecture of bit-serial polynomial basis (PB) multipliers over the binary extension field GF(^2m) generated by irreducible trinomials is presented. Bit-serial GF(^2m) PB multiplication offers a performance/area trade-off that is very useful in resource constrained applications. The architecture here proposed is based on LFSR (Linear-Feedback Shift Register) and can perform a multiplication in m clock cycles with a constant propagation delay of T_A + T_X. These values match the best time results found in the literature for bit-serial PB multipliers with a slight reduction of the space complexity. Furthermore, the proposed architecture can perform the multiplication of two operands for t different finite fields GF(^2m) generated by t irreducible trinomials simultaneously in m clock cycles with the inclusion of t(m - 1) flipflops and tm XOR gates.

Item Type:Article
Additional Information:

© 2021 Institute of Electrical and Electronics
This work was supported in part by the Spanish MINECO and CM under Grant S2018/TCS-4423, Grant TIN 2015-65277-R, and Grant RTI2018-093684-B-I00.

Uncontrolled Keywords:Multiplication; Architectures; Multipliers; LFSR; Bit-serial; GF(^2m); Polynomial basis; Trinomials
Subjects:Sciences > Computer science > Artificial intelligence
ID Code:63571
Deposited On:14 Jan 2021 18:38
Last Modified:15 Jan 2021 07:58

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