Low-delay FPGA-based implementation of finite field multipliers

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Imaña Pascual, José Luis (2021) Low-delay FPGA-based implementation of finite field multipliers. IEEE Transactions on circuits and systems II-express briefs, 68 (8). pp. 2952-2956. ISSN 1549-7747

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Official URL: http://dx.doi.org/10.1109/TCSII.2021.3071188




Abstract

Arithmetic operations over binary extension fields GF(2^m) have many important applications in domains such as cryptography, code theory and digital signal processing. These applications must be fast, so low-delay implementations of arithmetic circuits are required. Among GF(2^m) arithmetic operations, field multiplication is considered the most important one. For hardware implementation of multiplication over binary finite fields, irreducible trinomials and pentanomials are normally used. In this brief, low-delay FPGA-based implementations of bit-parallel GF(2^m) polynomial basis multipliers are presented, where a new multiplier based on irreducible trinomials is given. Several post-place and route implementation results in Xilinx Artix-7 FPGA for different GF(2^m) finite fields are reported. Experimental results show that the proposed multiplier exhibits the best delay, with a delay improvement of up to 4.7%, and the second best Area x Time complexities when compared with similar multipliers found in the literature.


Item Type:Article
Additional Information:

©2021 IEEE
This work was supported by the Spanish MINECO and CM under Grant S2018/TCS-4423 and Grant RTI2018-093684-B-I00.

Uncontrolled Keywords:Parallel; Complexity; Multipliers; Bit-parallel; Galois fields; Polynomial basis; Trinomials
Subjects:Sciences > Computer science > Artificial intelligence
ID Code:68150
Deposited On:11 Oct 2021 15:38
Last Modified:13 Oct 2021 07:22

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