Reliability of Error Correction Codes Against Multiple Events by Accumulation



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Clemente Barreira, Juan Antonio and Rezaei, Mohammadreza and Franco Peláez, Francisco Javier Reliability of Error Correction Codes Against Multiple Events by Accumulation. IEEE Transactions on Nuclear Science, 69 (2). pp. 169-180. ISSN 0018-9499

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Modern nanoscale devices with storage capacity typically implement error correction codes (ECCs) in order to cope with the effects of natural radiation. Thus, different state-of-the-art ECC techniques aim at preventing data corruption when different numbers of errors (or bitflips) occur in the same logical memory word. However, even though bit interleaving prevents a single particle (such as a proton or a neutron) from flipping several cells in the same word, it cannot be discarded that two independent events may affect nearby cells in the same word and, therefore, would provoke a multiple bit upset (MBU) or equivalent. This article studies the reliability of various state-of-the-art ECC techniques designed for memories to maintain their data integrity under radiation or any other hazardous conditions, where said event accumulation is likely to occur. For this purpose, a set of easy-to-use equations will be provided to estimate the probability of error occurrence in a memory that implements different ECCs, as a function of the number of accumulated bitflips, size of the memory, and word size.

Item Type:Article
Uncontrolled Keywords:Single Event Effects, Multiple Bit Upsets, Error Correction Codes, SRAM
Subjects:Sciences > Physics > Electronics
Sciences > Physics > Nuclear physics
Sciences > Computer science > Hardware
Sciences > Computer science > Electronics
ID Code:70718
Deposited On:24 Feb 2022 09:27
Last Modified:24 Feb 2022 09:27

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