Publication: Efficient hardware arithmetic for inverted binary ring-LWE based post-quantum cryptography
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2022-05-02
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IEEE-Inst Electrical Electronics Engineers Inc.
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Abstract
Ring learning-with-errors (RLWE)-based encryption scheme is a lattice-based cryptographic algorithm that constitutes one of the most promising candidates for Post-Quantum Cryptography (PQC) standardization due to its efficient implementation and low computational complexity. Binary Ring-LWE (BRLWE) is a new optimized variant of RLWE, which achieves smaller computational complexity and higher efficient hardware implementations. In this paper, two efficient architectures based on Linear-Feedback Shift Register (LFSR) for the arithmetic used in Inverted Binary Ring-LWE (InvBRLWE)-based encryption scheme are presented, namely the operation of A center dot B+C over the polynomial ring ${Z}_q/(x<^>n+1)$ . The first architecture optimizes the resource usage for major computation and has a novel input processing setup to speed up the overall processing latency with minimized input loading cycles. The second architecture deploys an innovative serial-in serial-out processing format to reduce the involved area usage further yet maintains a regular input loading time-complexity. Experimental results show that the architectures presented here improve the complexities obtained by competing schemes found in the literature, e.g., involving 71.23% less area-delay product than recent designs. Both architectures are highly efficient in terms of area-time complexities and can be extended for deploying in different lightweight application environments.
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©2022 IEEE
The work of José L. Imaña was supported in part by the Spanish Government Ministerio de Economia y Competitividad (MINECO) under Grant RTI2018-093684-B-I00 and in part by the Comunidad de Madrid under Grant S2018/TCS-4423. The work of Jiafeng Xie was supported by the National Science Foundation (NSF) Award under Grant SaTC-2020625 and Grant NIST-60NANB20D203.