Publication: Efficient hardware implementation of finite field arithmetic AB + C for Binary ring-LWE based post-quantum cryptography
Loading...
Official URL
Full text at PDC
Publication Date
2022-04
Advisors (or tutors)
Editors
Journal Title
Journal ISSN
Volume Title
Publisher
IEEE Institute of Electrical and Electronics Engineers
Citations
Exportar
Abstract
Post-quantum cryptography (PQC) has gained significant attention from the community recently as it is proven that the existing public-key cryptosystems are vulnerable to the attacks launched from the well-developed quantum computers. The finite field arithmetic AB + C, where A and C are integer polynomials and B is a binary polynomial, is the key component for the binary Ring-learning-with-errors (BRLWE)-based encryption scheme (a low-complexity PQC suitable for emerging lightweight applications). In this paper, we propose a novel hardware implementation of the finite field arithmetic AB + C through three stages of inter-dependent efforts: (i) a rigorous mathematical formulation process is presented first; (ii) an efficient hardware architecture is then presented with detailed description; (iii) a thorough implementation has also been given along with the comparison. Overall, (i) the proposed basic structure (u = 1) outperforms the existing designs, e.g., it involves 55.9% less area-delay product (ADP) than [13] for n = 512; (ii) the proposed design also offers very efficient performance in time-complexity and can be used in many future applications.
Description
(c) 2022 IEEE Institute of Electrical and Electronics Engineers
The work of Jiafeng Xie was supported by the NSFAward under Grants 2020625 and NIST-60NANB20D203. The work of Jose L. Imaña was supported by the Spanish MINECO and CM under Grants S2018/TCS-4423 and RTI2018-093684-B-I00.