Publication: Implementación paramétrica altamente segmentada del algoritmo k-means para la clusterización de imágenes hiperespectrales sobre hardware reconfigurable
Loading...
Official URL
Full text at PDC
Publication Date
2022
Authors
Advisors (or tutors)
Editors
Journal Title
Journal ISSN
Volume Title
Publisher
Citations
Exportar
Abstract
Este proyecto consiste en el diseño e implementación hardware del algoritmo de clusterización k-means, aplicado a imágenes hiperespectrales. El objetivo es lograr el cómputo en tiempo real, gracias a las técnicas de aceleración aplicadas.
El diseño cuenta con una arquitectura en pipeline altamente segmentado, compuesto por tres módulos retroalimentados entre sí, los cuales procesan de forma iterativa los datos de entrada hasta que los resultados convergen a valores estáticos.
Dicho pipeline opera con multitud de píxeles simultáneamente, además todas las bandas de cada píxel hiperespectral se tratan en paralelo. En consecuencia, este logra un rendimiento excepcional: es capaz de procesar a razón de un píxel hiperespectral completo por ciclo de reloj, de forma constante.
El diseño es completamente paramétrico, tal que es posible adaptarlo de forma automática a imágenes de distintas características o alterar las propiedades de la clusterización. También cuenta con una interfaz AXI Stream para facilitar su reutilización e integración en diversos sistemas.
Los resultados muestran una velocidad de procesamiento de aproximadamente 100 millones de píxeles hiperespectrales (con 224 bandas cada uno) por segundo con un discreto uso de recursos en FPGA. Se logra así un amplio margen para la ejecución del algoritmo en tiempo real, dejando holgura para los crecientes flujos de datos que trae la tecnología.
This project consists of creating a hardware design which implements the k-means clustering algorithm, applied to hyperspectral images. The goal is to achieve real-time computation, thanks to the acceleration techniques applied. The design has a deep pipelined architecture, made up of three modules with feedback between them, which iteratively process the input data until the results converge to static values. The pipeline operates with multiple pixels simultaneously, meanwhile all bands of each hyperspectral pixel are processed in parallel. As a result: it attains an exceptional performance, being able to reach a constant throughput of one full hyperspectral pixel per clock cycle. The design is fully parametric, so is possible to automatically adapt it to different kinds of images or to alter the clustering properties. Furthermore, it has an AXI Stream interface in order to increase its reusability and make it easier to integrate into different systems. The results reveal a processing speed of approximately 100 million hyperspectral pixels (with 224 bands each) per second with a discrete use of FPGA resources. This provides a wide margin for real-time execution of the algorithm, while leaving extra room for the increasing data flows brought by the newest technology.
This project consists of creating a hardware design which implements the k-means clustering algorithm, applied to hyperspectral images. The goal is to achieve real-time computation, thanks to the acceleration techniques applied. The design has a deep pipelined architecture, made up of three modules with feedback between them, which iteratively process the input data until the results converge to static values. The pipeline operates with multiple pixels simultaneously, meanwhile all bands of each hyperspectral pixel are processed in parallel. As a result: it attains an exceptional performance, being able to reach a constant throughput of one full hyperspectral pixel per clock cycle. The design is fully parametric, so is possible to automatically adapt it to different kinds of images or to alter the clustering properties. Furthermore, it has an AXI Stream interface in order to increase its reusability and make it easier to integrate into different systems. The results reveal a processing speed of approximately 100 million hyperspectral pixels (with 224 bands each) per second with a discrete use of FPGA resources. This provides a wide margin for real-time execution of the algorithm, while leaving extra room for the increasing data flows brought by the newest technology.
Description
Trabajo de Fin de Máster en Ingeniería Informática, Facultad de Informática UCM, Departamento de Arquitectura de Computadores y Automática, Curso 2021-22.