PERCIVAL: Open-source posit RISC-V core with quire capability



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Mallasén Quintana, David and Murillo Montero, Raúl and Barrio García, Alberto Antonio del and Botella Juan, Guillermo and Prieto Matías, Manuel (2022) PERCIVAL: Open-source posit RISC-V core with quire capability. IEEE transactions on emerging topics in computing, 10 (3). pp. 1241-1252. ISSN 2168-6750

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The posit representation for real numbers is an alternative to the ubiquitous IEEE 754 floating-point standard. In this work, we present PERCIVAL, an application-level posit RISC-V core based on CVA6 that can execute all posit instructions, including the quire fused operations. This solves the obstacle encountered by previous works, which only included partial posit support or which had to emulate posits in software. In addition, Xposit, a RISC-V extension for posit instructions is incorporated into LLVM. Therefore, PERCIVAL is the first work that integrates the complete posit instruction set in hardware. These elements allow for the native execution of posit instructions as well as the standard floating-point ones, further permitting the comparison of these representations. FPGA and ASIC synthesis show the hardware cost of implementing 32-bit posits and highlight the significant overhead of including a quire accumulator. However, results show that the quire enables a more accurate execution of dot products. In general matrix multiplications, the accuracy error is reduced up to 4 orders of magnitude. Furthermore, performance comparisons show that these accuracy improvements do not hinder their execution, as posits run as fast as single-precision floats and exhibit better timing than double-precision floats, thus potentially providing an alternative representation.

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©2022 This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.
This work was supported by a 2020 Leonardo Grant for Researchers and Cultural Creators, from BBVA Foundation, whose id is PR2003 20/01, by the EU(FEDER) and the Spanish MINECO under grant RTI2018-093684-B-I00, and by the CM under grant S2018/TCS-4423.

Uncontrolled Keywords:Standards; Hardware; Open area test sites; Arithmetic; Open source software; Registers; Field programmable gate arrays; Arithmetic; Posit; IEEE-754; Floating point; RISC-V; CPU; CVA6; LLVM; Matrix multiplication
Subjects:Sciences > Computer science > Artificial intelligence
ID Code:74813
Deposited On:04 Oct 2022 11:52
Last Modified:04 Oct 2022 13:14

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