Work-in-progress: High-performance systolic hardware accelerator for RBLWE-based post-quantum cryptography



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Bao, Tianyou and Imaña Pascual, José Luis and He, Pengzhou and Xie, Jiafeng (2022) Work-in-progress: High-performance systolic hardware accelerator for RBLWE-based post-quantum cryptography. In 2022 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). Institute of Electrical and Electronics Engineers., Nueva Jersey (EE.UU), pp. 5-6. ISBN 978-1-6654-7294-4

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Ring-Binary-Learning-with-Errors (RBLWE)-based post-quantum cryptography (PQC) is a promising scheme suitable for lightweight applications. This paper presents an efficient hardware systolic accelerator for RBLWE-based PQC, targeting highperformance applications. We have briefly given the algorithmic background for the proposed design. Then, we have transferred the proposed algorithmic operation into a new systolic accelerator. Lastly, field-programmable gate array (FPGA) implementation results have confirmed the efficiency of the proposed accelerator.

Item Type:Book Section
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International Conference On Hardware/Software Codesign And System Synthesis (CODES+ISSS) (2022. Shanghay)
ISSN: 2832-6466; ISSN e-:2832-6474
J. Xie was supported by NSF SaTC-2020625 and in part by NIST-60NANB20D203. J.L. Imaña was supported by PID2021-123041OB-I00 funded by MCIN/AEI/10.13039/501100011033 and by “ERDF A way of making Europe”, and by the CM under grant S2018/TCS-4423.

Uncontrolled Keywords:Polynomial multiplication; PQC; RBLWE; Systolic hardware accelerator
Subjects:Sciences > Computer science > Artificial intelligence
ID Code:76308
Deposited On:23 Jan 2023 16:35
Last Modified:23 Jan 2023 16:35

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