Publication: Diseño y caracterización de un procesador sintetizable de ultra-bajo consumo para sistemas empotrados multimedia
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2008
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Abstract
In the last years, VLIW processors are becoming a preferable solution for all those applications where high performance and low power consumption are needed. Therefore, this is a common need in embedded systems running multimedia applications. Several architectures and VLIW processors have been proposed lately in the specialized literature. One of these architectures is the VEX processor, which integrates simplicity and efficiency. In this Project, we have used for our experimental work a VEX-like architecture designed using the LISATek environment. The baseline architecture presented several limitations that showed out in the way of instruction hazards during the execution of the applications. One of the mail goals of our work was to detect those hazards and propose two different approaches to correct them. The first approach has been to develop a code parser that rewrites the code generated by the compiler and avoids the instruction hazards. While it is a straightforward approach, this technique limits the processor performance by reducing the parallelism of the code. The impact on performance has been also evaluated in our work. The code parser has been developed in C++ to be executed in UNIX environments The second approach was to add some hardware profiling registers to determine why these instruction hazards happen and allow further projects to do the needed reengineering of the architecture.